1. Field of the Invention
The embodiments of the invention generally relate to compact models for semiconductor devices and, more particularly, to a method for generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment.
2. Description of the Related Art
A compact model generally represents the electrical and physical behavior of an electronic device in its various operation modes. These compact models are incorporated into simulators to represent the various active and passive components of a semiconductor technology (e.g., a circuit). Compact models provide a powerful tool for predicting accurate circuit behaviors. Therefore, accurate compact models are essential. However, variations in the manufacturing line and deviations from the standard semiconductor process steps sometimes result in differences between the electrical parameters represented in the compact models and those actually present during the manufacturing process. Therefore, when circuit designers conduct model-to-hardware correlation studies to understand how simulations and hardware measurements compare, “model overrides” (i.e., adjustments) are made to the compact model parameters in order to match actual parameter measurements taken from the hardware under study. These overrides allow designers to analyze and assess the impact of manufacturing variations and to predict potential circuit problems.
Model to hardware correlation studies typically employ simulations to solve for a limited set of parameters, for example, as illustrated in U.S. Pat. No. 6,934,671 issued to Bertsch et al. on Aug. 23, 2005 and incorporated herein by reference. These studies operate using fixed equations and a small fixed set of device sizes in order to discover the model overrides for the supported parameters. Such restrictions limit the effectiveness of the model override values. Furthermore, such studies are generally time-consuming and complicated. Therefore, there is a need in the art for a fast and efficient method of generating compact model parameter overrides (i.e., of producing customized compact model parameters that represent a semiconductor device at the chip, wafer or multi-wafer level in a manufacturing environment).